PIPELINING: Structural Hazard example
A structural hazard would for example result from memory access of
instruction fetch and memory access of data, were it not for
separate data and instruction caches:
- data hazards (solved by forwarding)
- control hazards (loops, branches, etc.) solved by determining whether or
not the branch is taken and the target, earlier in the pipeline
(e.g. test for BEQ or BNE opcodes by the end of the instruction decode
register setup cycle: zero test hardware with additional adder inside
the instruction decoder rather than waiting until the ALU stage
of the pipeline).
- structural hazards (same part of microprocessor, e.g. registers, accessed)
accessing same parts of silicon: resource conflicts.
solved by such methods as using separate instruction cache (for FETCH)
and separate data cache for MEM.
another example of a structural hazard is when decoding (setting up input
registers) makes reference to same register as a register write: