pipelining: beyond 5 stages...
some practical examples of alternatives to the basic 5 stage pipeline
the MIPS R4000 (as in sgi workstations, NUMAchine, etc.) is 8 stage pipe:
"fetch" is 2 stages instead of 1,
and "memory" is 3 instead of 1 (3 total extra).
data value is avail after 2nd stage of "memory" so forwarding can be done with
delay 2 (directly to the ALU):
(as compared to delay of 1 with 5 stage pipe)
this structure of pipe helps with the cache architecture; caches to be
described later in course, in detail...
another example of something different:
it's somewhere between CISC and VLIW
127 64bit registers
instructions are 256 bits
HP+intel joint venture
gnux (gnu linux) is currently running on it native
but nobody could get win64 to run on it.